1. Technical Field
The disclosure relates generally to integrated circuit (IC) chip fabrication, and more particularly, to non-destructive, below-surface defect rendering of an IC chip using image intensity analysis.
2. Background Art
Given the existing trends within the semiconductor industry, today's Integrated circuit (IC) chips continually shrink in dimension and increase in complexity. Current state-of-the-art IC chip technology can have upwards of 10 metal levels and multiple dielectric materials. This evolutionary process, however, allows for new opportunities for failure analysis as the very nature and construction of the hardware changes.
One opportunity, as disclosed by Gignac et al. includes detecting sub-surface defects using a transmission electron microscope (TEM) with a scanning attachment by collecting backscattered electrons (BSE) with an accelerating voltage on the order of 30-400 keV. This approach of using a high beam energy makes changes in intensity in the patterned copper metal easily recognizable by the human eye, but requires custom built analytical equipment, Another process, such as disclosed in U.S. Pat. No. 6,366,688 to Jun et al., uses a scanning electron microscope (SEM) to evaluate a surface of an IC chip. This approach, however, is limited to evaluation of a surface, and does not address sub-surface defects.